As the dimensions of semiconductor devices and components continue to decrease, the need for increased alignment control between various layers or features within a single layer of a given sample will continue to increase. In the context of semiconductor processing, semiconductor-based devices may be produced by fabricating a series of layers on a substrate, some or all of the layers including various structures. The relative position of these structures both within a single layer and with respect to structures in other layers is critical to the performance of the devices.
Metrology processes are used at various steps during a semiconductor manufacturing process to monitor and control one or more semiconductor layer processes. For example, metrology processes are used to measure one or more characteristics of a wafer, such as dimension (e.g., line width, thickness, etc.) of features formed on the wafer during a process step, wherein the quality of the process step can be determined by measuring the one or more characteristics. One such characteristic includes overlay error.
An overlay measurement generally specifies how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it or how accurately a first pattern aligns with respect to a second pattern disposed on the same layer. The overlay error is typically determined with an overlay target having structures formed on one or more layers of a work piece (e.g., semiconductor wafer). If the layers or patterns of a given semiconductor device are not properly formed, then the structure on one layer or pattern tends to be offset or misaligned relative to the structure on the other layer or pattern. The misalignment between any of the patterns used at different stages of semiconductor integrated circuit manufacturing is known as ‘overlay error.’
In a general sense, metrology applications, such as overlay measurements, require high quality optics in order to satisfy the requirements of advanced lithography processes. In the case of overlay metrology, optical imperfections (e.g., aberrations) in the optical components of an implementing system may result in Tool Induced Shift (TIS). In this manner, optical imperfections in an optical system may cause a shift in the measured overlay relative to the actual overlay. For example, optical aberrations present in an optical column of a metrology may lead to TIS. The standard measurement of TIS involves measuring overlay at first position and then rotating the wafer by 180 degrees and repeating the overlay measurement. As such, TIS may be defined as:
                              T          ⁢                                          ⁢          I          ⁢                                          ⁢          S                =                              1            2                    ⁡                      [                                          OVL                ⁡                                  (                                      180                    ⁢                    °                                    )                                            +                              OVL                ⁡                                  (                                      0                    ⁢                    °                                    )                                                      ]                                              (                  Eq          .                                          ⁢          1                )            
where OVL(0°) represents the overlay measured at a first position and OVL(180°) is the measured overlay following 180 degree rotation of the sample relative to the first position.
Conventionally, there exists two ways in which to eliminate or limit the existence of TIS. First, expensive high-end optical components may be utilized in an implementing metrology system in order to help avoid the optical imperfections which lead to TIS. Second, upon measuring TIS within a given system, the given system may be calibrated in order to correct for the observed TIS level. Due to the calibration requirements, the existence of TIS leads to reduced throughput of a given semiconductor fabrication process. Moreover, the need for high-end optical components in order to avoid or limit TIS leads to increased cost of semiconductor processing and metrology. Accordingly, it may be desirable to provide a method and/or system which provide a more efficient TIS measurement process as well as an improved optical system which reduces the amount of TIS in a given system.